1. Field of the Invention
This invention relates to high resolution analog-to-digital and digital-to-analog converters, and in particular, to oversampled, noise shaping analog-to-digital and digital-to-analog converters.
2. Brief Description of the Related Technology and Prior Art
The use of sigma-delta modulators in analog-to-digital (A/D) and digital-to-analog (D/A) converter circuits is increasing. It is well known in the art that so-called higher order sigma-delta modulators have an inherently higher signal-to-noise ratio than lower ordered sigma-delta modulators. For many practical applications, fourth-order sigma-delta modulators have become the higher-order modulator of choice because they strike an appropriate balance between analog circuit complexity and accompanying digital filtering complexity. Various fourth-order sigma-delta modulators for A/D circuits are described in the following applications assigned to the common assignee of the present invention: application Ser. No. 08/112,610, filed Aug. 26, 1993, entitled "Fourth-Order Cascaded Sigma-Delta Modulator;" application Ser. No. 08/147,062, filed Nov. 3, 1993, entitled "Fourth-Order Cascaded Sigma-Delta Modulator;" and application Ser. No. 08/171,091, filed Dec. 21, 1993, entitled "Fourth-Order Cascaded Sigma-Delta Modulator." Another fourth-order sigma-delta modulator is described by Karema, et al, in U.S. Pat. No. 5,061,928. The aforementioned applications describe sigma-delta modulators created by connecting two, second-order sigma-delta modulators, each such modulator being characterized as having two associated unit delays from input to output. In each of the above applications, a unique post-quantization network combines the output of the two, second-order sigma-delta modulators in a manner such that a single modulated multi-bit data stream, with fourth-order shaping, results. The modulators in all of the examples given above are characterized as having four unit delays from input to final output.
A need has developed for a fourth-order sigma-delta modulator with fewer than four unit delays from input to output in order to overcome disadvantages associated with those fourth-order modulators having four unit delays from input to output. Prior art fourth-order sigma-delta modulators implemented as A/D converters suffer from increased operational amplifier and post-quantization network complexity. Additionally, when such sigmadelta modulators are used in the feedback loop of such circuits as echo cancelers, stability may be difficult to obtain due to the amount of delay from input to output through the sigma-delta modulator.
The sigma-delta modulator of FIG. 1 is an example of a fourth-order sigma-delta modulator which is formed by connecting two, second-order sigma-delta modulators. This is similar to the fourth-order modulator described in U.S. Pat. No. 5,061,928 by Karema, et al. This modulator is characterized as a cascade of two second-order modulators. These second-order modulators are characterized as including two integrators each of which can be characterized as having the following transfer function: EQU H(z)=z.sup.-1 /(1-z.sup.-1)
As can be seen in the above equation, there is a single unit delay in such an integrator due to the z.sup.-1 term in the numerator. Additionally, such second-order modulators are also characterized as having a quantizer, which typically is used to quantize only the sign of the signal presented at its input. This is commonly modeled as a summing node where one input is the input to the quantizer (Q) and the other input is a noise source (E) which represents the quantization noise of the quantizer. Such a model is shown in FIG. 1 as Q.sub.1 and Q.sub.2. The overall transfer function of such a second-order modulator is typically given by the following equation: EQU y(z)=z.sup.-2 x(z)+E(z)(1-z.sup.-1).sup.2
where y(z) is the output of the modulator, x(z) is the sampled input to the modulator, and E(z) is the quantization noise of the quantizer within the modulator.
When two such second-order modulators are connected together as shown in FIG. 1, the transfer function at output y1(z) can be characterized by the following equation: EQU y.sub.1 (z)=z.sup.-2 x(z)+E.sub.1 (z)(1-z.sup.-1).sup.2
where x(z) is the sampled input to the modulator and E.sub.1 (z) is the quantization noise of quantizer Q.sub.1. Output y.sub.2 (z) can be characterized by the following equation: EQU y.sub.2 (z)=z.sup.-2 E.sub.1 (z)+KE.sub.2 (z)(1-z.sup.-1).sup.2
where E.sub.1 (z) is the quantization noise due to quantizer Q.sub.1, K is a constant that is frequently used as a scaling factor for the connection between the first and second modulator, and E.sub.2 (z) is the quantization noise due to the quantizer Q.sub.1.
The two modulator outputs, y.sub.1 (z) and y.sub.2 (z) are typically combined using a post-quantization network which results in a final modulator output y.sub.out (z). An appropriate post-quantization network for use with the circuit of FIG. 1 is shown in FIG. 2. Such a circuit along with the two, second-order sigma-delta modulators shown in FIG. 1 will result in an overall fourth-order sigma-delta modulator which may be characterized by the following equation: EQU y.sub.out (z)=z.sup.-4 x(z)+KE.sub.2 (z)(1-z.sup.-1).sup.4
Essentially, the post-quantization circuit of FIG. 2 removes the quantization noise E.sub.1 (z) due to quantizer Q.sub.1. It also results in an overall fourth-order high pass filtering function on the quantization noise E.sub.2 (z) due to quantizer Q.sub.2. As can be seen in the above equation, such a modulator has an overall constant group delay of four sample periods due to the z.sup.-4 term in front of the x(z) term.
In application Ser. No. 08/147,062, described previously, a fourth-order sigma-delta modulator is formed by connecting two, second-order sigma-delta modulators together such that only the input of the first quantizer is fed to the second, second-order sigma-delta modulator. The output of each quantizer for each second-order sigma-delta modulator is then fed to a post-quantization network which removes the quantization noise of the first, second-order sigma-delta modulator and shapes the quantization noise of the second, second-order sigma-delta modulator with a fourth-order high pass filter function. Such a sigma delta modulator is shown in FIGS. 3 and 4 and can be characterized by the same equation that characterizes the operation of the fourth-order sigma-delta modulator described by Karema, et al. That is, the output of the fourth-order sigma-delta modulator described in the aforementioned application also has a constant group delay of four sample periods.
It is an object of the present invention to provide a fourth-order sigma-delta modulator which has high resolution, but with an overall constant group delay of two sample periods. This is to be accomplished by connecting together two, second-order sigma-delta modulators, each being characterized as having an overall constant group delay of one sample period. An example of a prior art second-order modulator having unit delays less than one is described in the IEEE Journal of Solid State Circuits, Vol. 25, no. 4, Aug. 1990, pp. 979-986, in the article entitled "The Implementation of Digital Echo Cancellation in Codecs," by Friedman, et al. Friedman describes a second-order modulator characterized as having integrators with 1/2 unit delays from input to output. Furthermore, the second-order sigma-delta modulator of Friedman is characterized as requiring two flip-flops to perform delay functions in the feedback of the modulator to obtain the desired transfer function. Such a second-order sigma-delta modulator is shown in FIG. 5.
It is, therefore, a further object of the present invention to describe a second-order sigma-delta modulator which does not require two flip-flops in the feedback of the sigma-delta modulator, thus reducing the manufacturing cost of such a sigma-delta modulator.
It is a further object of the present invention to utilize two such second-order sigma-delta modulators, which are to be connected together, to form a portion of a fourth-order sigma-delta modulator.
It is still a further object of the present invention to connect two such second-order modulators to a post-quantization network to form an overall fourth-order sigma-delta modulator with a total of two unit sample delays.
It is yet another object of the present invention to provide a sigmadelta modulator which can be fabricated using switched capacitor circuitry in such a fashion as to form an A/D converter.
It is still another object of the present invention to provide a sigmadelta modulator which can be used as a digital noise shaper for a D/A converter.